1. Field of the Invention
The present invention relates to a fabricating method for a flat panel display device, and more particularly to a fabricating method for a flat panel display device that is adapted to reduce its manufacturing cost.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) device controls the light transmittance of liquid crystal in accordance with a video signal, thereby displaying a picture. For this, the liquid crystal display device includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix shape, and a drive circuit for driving the liquid crystal display panel.
The liquid crystal display device is divided into two main classes in accordance with the direction of the electric field which drives the liquid crystal: a twisted nematic (TN) mode where a vertical electric field is used and an in-plane switch (IPS) mode where a horizontal electric field is used.
The TN mode is a mode in which the liquid crystal is driven by a vertical electric field between a pixel electrode and a common electrode respectively arranged on the lower and upper substrates. The TN mode device has an advantage in that its aperture ratio is relatively high but a disadvantage in that its viewing angle is relatively narrow. On the other hand, the IPS mode is a mode in which the liquid crystal is driven by a horizontal electric field between the pixel electrode and the common electrode arranged in parallel on the lower substrate. The IPS mode device has an advantage in that its viewing angle is relatively wide but a disadvantage in that its aperture ratio is relatively low.
FIG. 1 is a sectional diagram representing a TN mode liquid crystal display panel of the related art. In FIG. 1, the liquid crystal display panel includes an upper array substrate having black matrix 54, a color filter 56, a common electrode 68, and an upper alignment film 58 which are sequentially formed on an upper substrate 52. The panel also includes a lower array substrate having a thin film transistor (hereinafter, referred to as a “TFT”), a pixel electrode 66 and a lower alignment film 88 which are formed on a lower substrate 82. Liquid crystal 16 is injected into an inner space between the upper array substrate and the lower array substrate.
In the upper array substrate, the black matrix 54 defines a cell area where a color filter 56 is to be formed. The black matrix 54 prevents light leakage and absorbs external light to increase contrast. The color filter 56 is formed in the cell area which is defined by the black matrix 54. The color filter 56 is formed in R, G and B to realize a color picture of the liquid crystal display panel. A common voltage is supplied to the common electrode 68 to control the movement of the liquid crystal 16. In contrast to the TN mode in which the common electrode 68 is formed on the upper substrate 52 and the vertical electric field is used, in the IPS mode, the horizontal electric field is used, and the common electrode 68 is formed in the lower array substrate.
In the lower array substrate, the TFT includes a gate electrode 59 formed on the lower substrate 82 along with a gate line (not shown); semiconductor layers 64, 97 overlapping the gate electrode 59 with a gate insulating film 94 separating the semiconductor layers 64, 97 from the gate electrode 59; and source and drain electrodes 90, 92 formed over the semiconductor layers 64, 97 and spaced apart from each other. A data line (not shown) is formed along with the source/drain electrodes 90, 92. The TFT supplies a pixel signal from the data line to a pixel electrode 66 line in response to a scan signal from the gate line.
The pixel electrode 66 is formed over a passivation film 100 and is in contact with a drain electrode 92 of the TFT through a contact hole. The pixel electrode 66 is formed of a transparent conductive material with high light transmittance. The upper and lower alignment films 58, 88 for liquid crystal alignment are formed by a rubbing process after spreading an alignment material, such as polyimide, over the upper and lower substrates, respectively.
Thin film patterns, including the gate electrode 59, of the liquid crystal display panel are patterned by a photolithography process using a mask. FIGS. 2A to 2D are sectional diagrams representing the steps of forming a gate electrode using a photolithography process.
In FIG. 2A, a gate metal 59a and a photo-resist material 60 are deposited on a lower substrate 82 by a deposition method such as sputtering. A mask 61 with apertures aligned for each area where the gate electrode 59 is to be formed is placed on the photo-resist material 60. An exposure and development process is performed to form a photo-resist pattern 60a shown in FIG. 2B. An etching process is then performed to pattern the gate metal 59, as shown in FIG. 2C. Finally, as shown in FIG. 2D, the gate electrode 59 is completed with a stripping process to strip out the photo-resist pattern 60a. 
The photolithography process of the related art using the mask includes at least a photo-resist spreading process, a mask aligning process, an exposure and development process and an etching process. Thus, the related art process is complicated. Also, a substantial amount of photo-resist material and developing solution may be wasted during the process for developing the photo-resist pattern. Moreover, expensive equipment is used in the exposure process of the related art photolithography process.